A prior flash electrically erasable and programmable read-only memory ("flash EPROM") typically uses memory cells that include electrically isolated gates (i.e., floating gates). Information is stored in the memory cells in the form of charge on the floating gates. FIG. 1 illustrates the structure of one such memory cell 10. Memory cell 10 includes a drain region 13 and a source region 14 in a substrate 15. Source region 14 and drain region 13 are asymmetrically doped with an arsenic dopant and source region 14 is additionally doped with a phosphorous dopant. A polysilicon floating gate 12 is generally disposed above and between these regions and insulated from these regions by an insulating layer 16. Floating gate 12 at the completion of processing is completely surrounded by insulating layers and electrically floats. A second gate (i.e., a control gate) 11 is disposed above floating gate 12 that is fabricated from a second layer of polysilicon. A second insulating layer 17 separates floating gate 12 from control gate 11.
As can be seen from FIG. 2A, memory cell 10 is programmed (i.e., negatively charging the floating gate) by coupling control gate 11 to a gate programming potential of approximately +12 volts, drain region 13 to a drain programming potential of approximately +7 volts, and source region 14 to ground. Under these conditions, channel hot electron injection occurs through oxide layer 16. The electrons deposited on floating gate 12 of memory cell 10 cause the threshold voltage of memory cell 10 to rise. Memory cell 10 is now programmed to have a programmed threshold voltage V.sub.TP.
To erase cell 10, drain region 13 is floated, control gate 11 is grounded and an erasure potential of approximately +12 volts is applied to source region 14, as shown in FIG. 2B. Under these conditions, charge is tunneled from floating gate 12 to source region 14. This removes the electrons deposited on floating gate 12 of memory cell 10, causing the threshold voltage of memory cell 10 to decrease. Memory cell 10 is now erased to have an erased threshold voltage V.sub.TE.
To read cell 10, a positive read potential less than that which would cause charge to transfer onto floating gate 12 is applied to control gate 11 (e.g., 5 volts) and a potential (e.g., 1 volt) is applied to drain region 13. Current through the device is sensed to determine if floating gate 12 is or is not negatively charged.
The speed at which memory cell 10 is erased largely depends on the erasure ability of memory cell 10 and the erasure voltage applied to the source of memory cell 10. Typically, the higher the erasure voltage applied to the source of memory cell 10, the faster memory cell 10 is being erased. However, one disadvantage of such prior art erasure technique is that if the erasure voltage applied to the source of memory cell 10 exceeds certain voltage threshold (e.g., 12 volts), the source-to-gate junction of memory cell 10 then moves into the breakdown region, at which hot holes are generated in floating gate 12 of memory cell 10. This is detrimental to the lifetime cycles of the memory cell. Therefore, the erasure voltage constraint typically limits the increase in the erasure speed of memory cell 10. In addition, when the source-to-gate junction of memory cell 10 is at the breakdown condition, the erasure speed of memory cell 10 does not increase when the erasure voltage increases.